Every Azure chip Microsoft has built started as electronic design automation (EDA) jobs used to design, test, and validate silicon before it is manufactured. This includes simulation sweeps that run for days, verification regressions that fan out across thousands of cores overnight, and physical signoff runs that use hundreds of gigabytes of memory for a single block.
Together, these workloads account for hundreds of millions of compute jobs each year. Today we’re sharing early results from our next step in that evolution: running EDA workloads on Azure Cobalt 200 , Azure’s custom compute infrastructure built on the Arm Neoverse CSS V3. In our silicon design environment, the evaluated EDA workloads ran with 1.
30x to 4. 15x more performance than on Cobalt 100 across a range of testing scenarios, from simulation to verification to static timing analysis. Learn more about Azure Cobalt 200 VMs Traditionally, EDA workloads ran on fixed, on-premise x86 server capacity, sized for peak demand with periods of underutilization.
The shift to cloud-based EDA on Microsoft Azure offered a new level of flexibility, scale, and reliability on compute-intensive silicon design workloads. Using Azure Cobalt-based virtual machine (VM) instances, silicon engineering teams at Microsoft are experiencing significant performance and efficiency improvements on EDA workloads that Azure customers are seeing across many workloads—optimizing the performance and speed of designing increasingly sophisticated silicon for increasingly complex cloud systems.
In this blog, we highlight results from Cadence Xcelium and Cadence Spectre, Synopsys PrimeTime and Synopsys VCS, and Siemens Calibre tools. Tools enabled on Cobalt 100 ran unmodified in our Cobalt 200 evaluation, allowing us to focus on performance testing rather than functionality. Why Cobalt 200 suits EDA EDA spans workloads with very different compute requirements: Circuit and analog simulation — optimized for highly parallel workloads, with sensitivity to memory behavior.
Functional and formal verification — throughput-driven, with large numbers of independent jobs running concurrently. Implementation and signoff — memory-intensive and bandwidth-sensitive, with long-running jobs. For computer-aided design (CAD) managers, predictable per-core performance is essential to planning overnight regressions.
Per-core performance measured on a lightly loaded VM does not necessarily hold as concurrency increases. Verification farms need predictable throughput when VMs are heavily loaded. Cobalt 200 combines physical cores without the overhead of hyperthreading, dedicated 3MB L2 cache per core, and high provisioned memory bandwidth to support concurrent workloads.
These core and memory architecture characteristics support strong per-core performance at high utilization. What we measured We tested Cobalt 200 with workloads from several stages of Microsoft’s silicon development flow, including RTL and gate-level simulation, static timing, physical verification, and analog simulation, comparing job completion time with Cobalt 100 and selected x86 Azure VMs.
All tested VMs were configured with the maximum number of cores possible for high throughput 5 , multiple jobs were concurrently executed on the VM to validate the performance under high load conditions. Throughput is normalized per logical core. For the Cobalt 100, Cobalt 200, and hx176rs configurations, logical cores are also physical cores.
Consolidated EDA workload results Workload EDA tool Measure Cobalt 200 result Digital simulation Cadence Xcelium 1 Peak throughput per logical core More than 40% higher than any other tested system Digital simulation Synopsys VCS 1 Peak throughput per logical core More than 40% higher than any other tested system Analog and mixed-signal simulation Cadence Spectre 2 Throughput per logical core 38% higher generation over generation; exceeded tested x86 Azure VMs Physical verification Siemens Calibre 3 DRC Wall time / relative performance 23% lower wall time; 1.
30× relative performance versus Cobalt 100 Static timing analysis Synopsys PrimeTime 4 Peak throughput per logical core 2. 0× Cobalt 100; exceeded tested x86 Azure VMs Digital simulation Cadence Xcelium and Synopsys VCS are tools used to simulate and verify digital designs. RTL simulation is central to functional verification and can consume significant compute capacity as teams run large regression suites.
When testing RTL workloads using both simulators, optimally loaded Cobalt 200 systems delivered significantly greater peak throughput than the previous generation. For the workload tested on Xcelium and VCS, Cobalt 200 delivered more than 40% higher throughput per logical core than any other system we tested . Throughput is normalized per logical core to account for the VMs’ different core counts.
Cobalt 200 was optimized for EDA workloads through increased cache size and improved memory bandwidth per core. Our results demonstrate that Cobalt 200 design optimizations generate significantly improved performance for logic simulation workloads. Figure 1 and 2.
Cadence Xcelium RTL and Synopsys VCS simulation throughput for an internal real simulation test case, normalized jobs per hour per logical core; Cobalt 100 = 1. 0. Analog and mixed signal simulation Cadence Spectre is used for analog and mixed-signal circuit simulation.
Analog and mixed-signal circuit simulation workloads differ from RTL simulation and are dominated by multithreaded performance. We tested Cadence Spectre on Cobalt 200 and observed 38% higher throughput per logical core generation over generation, and delivered 11-52% higher throughput per logical core compared with all other platforms tested. Figure 3.
Cadence Spectre analog simulation throughput for an internal test case, normalized jobs per hour per logical core; Cobalt 100 = 1. 0. This result shows meaningful progress between Cobalt generations.
Originally published at azure.microsoft.com
